1. Field of the Invention
The present invention generally relates to retrieving data from memory before the data has been requested by an electrical device.
2. Background Information
Conventional computer systems, and other types of electronic systems, have memory that generally is accessible by a variety of system components. Such system components may include microprocessors, network interface controllers, graphics subsystems, etc. To facilitate the efficient interaction with memory by such components, a typical system may include a memory controller. The memory controller may provide a mechanism through which various system components can issue read and/or write requests to memory. The memory controller includes arbitration logic to determine which request, of multiple pending memory requests, should next be granted access to memory. Numerous examples of memory controllers and arbitration logic are available. See e.g., U.S. Pat. Nos. 6,269,433, 6,226,755, and 6,233,661, all of which are incorporated herein by reference.
The transfer of a command or data message across a bus may require the coordination of various control signals to initiate the cycle, claim the cycle, and complete the cycle. Core logic, such as that included in microprocessors, typically operates at higher clock rates than the busses to which the devices connect. In general terms, a microprocessor receives and processes data or writes data at a much faster pace than the memory and the busses interconnecting the microprocessor and memory, can function to transfer the data. As such, the operational bottleneck often is the transfer rate of data across the system's busses. Thus, improvements which expedite the transfer of data to or from memory may be desirable.